With the increasement of complexity of software executed in processors, software debugging and implementation effect of analysis software become more and more important and collecting path information of program execution is of important significance. There are two common path information collection methods. The first is to simulate and execute a program by a simulator, which is simple to implement, but the slow emulation speed affects the efficiency of information collection. The second is to embed a hardware module in the processor to record path information in real time, which has a fast speed of information collection, but the on-chip memory size and the data transmission bandwidth limits the amount of information to be recorded. In order to increase the efficiency of information collection, and reduce requirement on hardware conditions at the same time, an efficient program counter compression method is desired to reduce the amount of effective data to be recorded.
Since the program counter compression module is not a core component of the processor, its hardware resource consumption should be as small as possible, and its power consumption should be as low as possible in order not to influence the overall area and performance of the processor. Therefore, exploring an efficient program counter compression scheme and a hardware circuit thereof to increase compression ratio of the program counter and reduce resource consumption and power consumption of the hardware module has important research value.
Existing program counter compression methods are proposed mainly based on two points of view/angle. The first is the compression based on architecture, for example, only records jump instruction information in the execution of program and does not process sequence instruction information. The second is a common loseless data compression method such as differential encoding and dictionary coding. Most prior art technologies have not combined the two angle effectively and the compression effect is still to be improved. In the aspect of architecture compression, existing research paied less attention to obstruction instructions, which impacts compression effect in some particular fields. Dictionary coding has been widely applied in the compression of program counter. However, most hardware implementation methods for dictionary coding proposed in existed research require much hardware resource, particularly more registers, and require large power consumption at the same time, which limits the practical application of this method.